1. Field of the Invention
The present invention relates to semiconductor non-volatile memory, and more particularly to a non-volatile semiconductor memory device having a charge storage layer.
2. Description of the Prior Art
Non-volatile memory is a type of memory that retains information it stores even when no power is supplied to memory blocks thereof. Some examples include magnetic devices, optical discs, flash memory, and other semiconductor-based memory topologies. Some forms of non-volatile memory have bits defined in fabrication, some may be programmed only once (one time programmable ROM, OTP ROM), and other types may be programmed and reprogrammed many times over. As semiconductor memory technologies have matured, one advantage that has come out of development of such technologies is the ability to integrate substantial amounts of memory cells in integrate circuits (ICs). However, it is desirable that the memory cells be formed in the same process with the ICs.
One goal of non-volatile memory devices is to fit increasing numbers of memory cells in smaller chip areas while utilizing the same fabrication process as other complementary metal-oxide-semiconductor (CMOS) devices in the IC. One method for increasing the number of memory cells utilizes “charge storage structures” to form 2-bit non-volatile semiconductor memory transistors. Please refer to FIG. 1, which is a diagram of a semiconductor memory transistor 100 according to the prior art. The semiconductor memory transistor 100 is formed on a substrate, which has two implanted source/drain regions 157-1 and 157-2 and a channel region 156. The channel region 156 and the implanted source/drain regions 157-1, 157-2 are formed under a gate region 152, and two charge storage structures 155-1 and 155-2 formed on either side of the gate region 152. The charge storage structures 155-1, 155-2 are made of a spacer material that has charge trapping properties, e.g. silicon-nitride or a high-k dielectric. The charge storage structure 155-2 is programmed by applying a gate voltage VG of 5 Volts and a drain voltage V2 of 5 Volts, with a source voltage V1 of 0 Volts. Thus, channel hot electrons from the source region 157-1 may enter the charge storage region 155-2 by traveling through the channel region 156. To erase the charge storage structure 155-2, a gate voltage VG of −5 Volts and a drain voltage V2 of −5 Volts may be applied, inducing band-to-band tunneling holes to enter the charge storage structure 155-2.
Another technique for providing a CMOS non-volatile memory cell that is fabricated using standard CMOS processes is shown in FIG. 2, which is a diagram of a CMOS non-volatile memory cell 200 (“memory cell 200” hereinafter) according to the prior art. The memory cell 200 is fabricated on a substrate 202, has two source/drain regions 204-1 and 204-2, and two poly gates 206-1 and 206-2 separated from the substrate 202 by gate dielectric layers 208-1 and 208-2, respectively. The gate dielectric layers 208-1/208-2 are formed of oxide-nitride-oxide (ONO) material. A programming layer 210 is formed between the two poly gates 206-1, 206-2, and is isolated from the two poly gates 206-1, 206-2 by an isolating layer 212. The programming layer 210 provides charge storage similar to a silicon-oxide-nitride-oxide-silicon (SONOS) structure utilized in flash memory cells. However, in the CMOS non-volatile memory cell 200, the two poly gates 206-1, 206-2 are utilized to program the programming layer 210. Silicon-nitride sidewall spacers 214-1 and 214-2 are deposited with the programming layer 210 for controlling e-field fringing near the source/drain regions 204-1, 204-2. Sidewall isolating layers 216-1 and 216-2 are grown with the isolating layer 212, and isolate the SiN sidewall spacers 214-1, 214-2 from the poly gates 206-1, 206-2 and the substrate 202. Second sidewall spacers 218-1, 218-2 are formed from silicon oxide. The programming layer 210 is programmed by grounding the poly gate 206-1, and leaving the source/drain regions 204-1, 204-2 and substrate 202 floating. A high voltage is applied to the poly gate 206-2 to attract electrons from the poly gate 206-1 into the programming layer 210 through the isolating layer 212. The negative charge of the programming layer 210 over the channel causes a negative bias, increasing threshold voltage of the memory cell 200 relative to non-programmed transistors in the same circuit.
Many various topologies are provided in the prior art for forming memory cells with charge storage layers. However, the memory cells are slow and inefficient.